Based on 2102 1K*1 SRAM chips.
This board model was one of the first entries into the Altair-compatible or "S100" market after the initial release of the Altair 8800.
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Based on 2102 1K*1 SRAM chips.
This board model was one of the first entries into the Altair-compatible or "S100" market after the initial release of the Altair 8800.
Two banks of 2107 4K*1 DRAM chips.
Early DRAM boards for the Altair/S100 were notorious for a lack of reliability due to poor design.
This board model seems to have escaped this reputation, thanks to a design that interleaves refresh
into the 2MHz 8080 processor cycle in such a manner as to avoid conflict with memory access cycles,
and with no wait-states.
Based on 2102 1K*1 SRAM chips.
Another early entry into the competitive S100 market from one of the smaller manufacturers.
Date codes on ICs are 1977-78.
This board features configurable Write-Protection, selectable 0 or 1 Wait States, and can respond to the S100 PHANTOM signal.
Note: This board controls S100.pRDY while addressed, and actively drives it HIGH.
The control of pRDY is intended for 1-Wait-state mode, but pRDY is affected even in 0-wait-state mode.
The active-drive-HIGH can conflict with other drivers of pRDY - in particular, front panels.
For 0-wait-state mode - where there is no actual need to control pRDY - that control can be removed by opening pin U9.11.
Nothing-but-ROM-read boards were not very prevalent in the S100 world.
ROM usually ended up being an additional function on CPU or disk-controller boards.
This is a simple ROM board design providing 2KB in a 2716. As presented, it occupies 4KB of address space, with the 2K overmapped into the 4K, but it could be readily modified for a 2nd 2716, a larger EPROM, or limiting the address space to 2K.
An active S100-bus terminator with a socket for use as an extender board as well.
The termination is a 470Ω resistor on each bus-line to a low-impedance, regulated, 3.2V source.
| S100 Miscellaneous | bhilpert 2024 Apr |